1. Field of the Invention
The present invention relates to a semiconductor device using a dynamically reconfigurable circuit technique.
2. Description of the Related Art
Recently, advance in functional complication and variety is made in apparatuses requiring low cost and low power consumption, such as a mobile apparatus. Thus, such an apparatus requires high function. In order to achieve both high function and low power consumption, a special hardware must be manufactured and developed. However, the foregoing advance in functional complication and variety is a factor of increasing the cost of manufacturing and developing the specific hardware year by year. A semiconductor device using a dynamically reconfigurable circuit technique has attracted interests as a device for reducing the cost of manufacturing and developing the special hardware.
The semiconductor device using a dynamically reconfigurable circuit technique is provided with a reconfigurable circuit such as FPGA and a storage. The storage stores a plurality of set information required for configuring a circuit (hereinafter, referred to as execution circuit) executed by the reconfigurable circuit. The foregoing semiconductor device is a device which reads circuit information necessary for an operation to configure an execution circuit according to a rule predetermined by software. The foregoing semiconductor device differs from the conventional semiconductor device using a FPGA in that the execution circuit is changed in an operation.
The foregoing semiconductor device is used, and thereby, the cost of developing a special hardware is reduced like the FPGA. In addition, the execution circuit is dynamically configured, and thereby, various functions are realizable on a small semiconductor device. Thus, it is expected to reduce the cost of manufacturing the special hardware.
The following examples are given as the semiconductor device using a dynamically reconfigurable circuit technique. One is NEC Electronics, DRP (Dynamically Reconfigurable Processor, ““Reconfigurable system”, Ohm Company, page 189-208. Another is University of Carnegie Melon, Piperench (“PipeRench: a reconfigurable architecture and compiler”, IEEE Computer volume 33, Issue 4, April 2000 page(s): 70-77”).
The DRP of NEC Electronics has the following configuration. According to the configuration, a basic element executing an operation, that is, PEs (Processing Elements) are arrayed tow-dimensionally, and a state transition controller is arranged on the center. The PE is an operation device capable of configuring an execution circuit. A command memory in the PE is stored with a plurality of set information such as a kind of operation and the connection relationship between PEs. Each PE reads set information from the command memory according to a command pointer given from the state transition controller, and then, dynamically configures an execution circuit.
The Piperench of University of Carnegie Melon has the following configuration. According to the configuration, a stripe comprising a basic element executing an operation, that is, a plurality of PEs and a bus connecting them are connected like a pipeline. The PE is an operation device capable of configuring an execution circuit, and connected with a controller existing outside the PipeRench via a global bus. PE set information such as a kind of operation and the bus connection relationship is transferred from the controller existing outside the PipeRench to the PE via the global bus. According to the foregoing information, the PE dynamically configures an execution circuit.
The following condition must be satisfied in order to realize a semiconductor device using a dynamically reconfigurable circuit, which has a high function, small area and low power consumption. Namely, when a semiconductor device executes processing, set information required for the next processing must be stored in a storage at a high speed as much as possible. Thus, even if the size of the storage previously included in the semiconductor device is small, various execution circuits are configurable on the semiconductor device without a big delay. Therefore, it is possible to realize a semiconductor device, which has a high function, small area and low power consumption.
However, the conventional semiconductor device using the dynamically reconfigurable circuit has the following problem. Specifically, the size of set information to be written to the storage for executing a processing is not sufficiently small. For this reason, when the semiconductor device executes a processing, it is difficult to sufficiently store set information required for the next processing.
The foregoing PipeRench and DRP have the following problem. Specifically, a set change of the semiconductor device is limited to a rough set change such as a change of operation kind; however, the size of set information is not sufficiently small.
The following method is given as a method of making small the size of set information written to the storage included in the semiconductor device using the dynamically reconfigurable circuit. According to the method, the storage of the semiconductor device is stored with set information compressing information by a compression coding capable of restoring the original set information (hereinafter, referred to as compression). Then, the set information is properly decoded when an execution circuit is configured.
However, the foregoing PipeRench and DRP have the following problem. Specifically, one controller concurrently gives instructions to configure an execution circuit to a plurality of dynamically reconfigurable circuits. For this reason, the number of the dynamically reconfigurable circuits controlled by the controller increases to some degree, and thereby, time is taken to decode. As a result, the processing performance of the semiconductor device is reduced.